Technical Document
Specifications
Brand
Texas InstrumentsMounting Type
Surface Mount
Package Type
TSSOP
Pin Count
16
Dimensions
5 x 4.4 x 1.15mm
Maximum Operating Supply Voltage
3.6 V
Maximum Operating Temperature
+85 °C
Minimum Operating Temperature
-40 °C
Minimum Operating Supply Voltage
1.65 V
Product details
74LVC Family Decoders/Multiplexers, Texas Instruments
Texas Instruments range of Decoders, Multiplexers and De-multiplexers from the 74LVC Family of Low-voltage CMOS Logic ICs. The 74LVC Family use silicon gate CMOS technology and is designed to operate at 3.3V, allowing a significant reduction in power consumption when compared to 5V systems.
Operating Voltage: 1.65 to 3.6V
5V tolerant inputs
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 250 mA per JESD 17
ESD protection exceeds JESD 22
74LVC Family
€ 31.95
€ 0.355 Each (In a Tube of 90) (Exc. Vat)
€ 38.66
€ 0.43 Each (In a Tube of 90) (inc. VAT)
90

€ 31.95
€ 0.355 Each (In a Tube of 90) (Exc. Vat)
€ 38.66
€ 0.43 Each (In a Tube of 90) (inc. VAT)
Stock information temporarily unavailable.
90

Stock information temporarily unavailable.
| Quantity | Unit price | Per Tube | 
|---|---|---|
| 90 - 360 | € 0.355 | € 31.95 | 
| 450 - 1710 | € 0.319 | € 28.71 | 
| 1800 - 4410 | € 0.287 | € 25.83 | 
| 4500+ | € 0.259 | € 23.31 | 
Technical Document
Specifications
Brand
Texas InstrumentsMounting Type
Surface Mount
Package Type
TSSOP
Pin Count
16
Dimensions
5 x 4.4 x 1.15mm
Maximum Operating Supply Voltage
3.6 V
Maximum Operating Temperature
+85 °C
Minimum Operating Temperature
-40 °C
Minimum Operating Supply Voltage
1.65 V
Product details
74LVC Family Decoders/Multiplexers, Texas Instruments
Texas Instruments range of Decoders, Multiplexers and De-multiplexers from the 74LVC Family of Low-voltage CMOS Logic ICs. The 74LVC Family use silicon gate CMOS technology and is designed to operate at 3.3V, allowing a significant reduction in power consumption when compared to 5V systems.
Operating Voltage: 1.65 to 3.6V
5V tolerant inputs
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 250 mA per JESD 17
ESD protection exceeds JESD 22
