Techniniai Dokumentai
Specifikacijos
Markė
STMicroelectronicsProduct Type
Microcontroller
Serija
STM32G491
Pakuotės tipas
BGA
Mount Type
Surface
Kaiščių skaičius
100
Device Core
ARM Cortex M4
Data Bus Width
32bit
Program Memory Size
512kB
Maximum Clock Frequency
48MHz
RAM Size
112kB
Maximum Supply Voltage
3.6V
DACs
4 x 12 Bit
Minimali darbinė temperatūra
-40°C
Analogue Comparators
4
Maksimali darbinė temperatūra
85°C
Aukštis
0.6mm
Ilgis
5.1mm
Standards/Approvals
No
Plotis
5.1mm
Minimum Supply Voltage
1.71V
Number of Timers
15
Instruction Set Architecture
RISC
Automotive Standard
No
ADCs
1 x 3 Bit
Program Memory Type
FLASH
Produkto Aprašymas
The STMicroelectronics 32 bit MCU has ADC1/2 can be used in dual mode ADC3 usable only in single mode. It has no parity check in SRAM 2.It has 512/256K single bank flash. The bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation.
Sandėlio informacija laikinai nepasiekiama.
€ 3 185,00
€ 6,50 Each (In a Tray of 490) (be PVM)
€ 3 853,85
€ 7,865 Each (In a Tray of 490) (su PVM)
490

€ 3 185,00
€ 6,50 Each (In a Tray of 490) (be PVM)
€ 3 853,85
€ 7,865 Each (In a Tray of 490) (su PVM)
Sandėlio informacija laikinai nepasiekiama.
490

Techniniai Dokumentai
Specifikacijos
Markė
STMicroelectronicsProduct Type
Microcontroller
Serija
STM32G491
Pakuotės tipas
BGA
Mount Type
Surface
Kaiščių skaičius
100
Device Core
ARM Cortex M4
Data Bus Width
32bit
Program Memory Size
512kB
Maximum Clock Frequency
48MHz
RAM Size
112kB
Maximum Supply Voltage
3.6V
DACs
4 x 12 Bit
Minimali darbinė temperatūra
-40°C
Analogue Comparators
4
Maksimali darbinė temperatūra
85°C
Aukštis
0.6mm
Ilgis
5.1mm
Standards/Approvals
No
Plotis
5.1mm
Minimum Supply Voltage
1.71V
Number of Timers
15
Instruction Set Architecture
RISC
Automotive Standard
No
ADCs
1 x 3 Bit
Program Memory Type
FLASH
Produkto Aprašymas
The STMicroelectronics 32 bit MCU has ADC1/2 can be used in dual mode ADC3 usable only in single mode. It has no parity check in SRAM 2.It has 512/256K single bank flash. The bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation.