Techniniai Dokumentai
Specifikacijos
Markė
onsemiProduct Type
18 Bit D Type Latch
Logic Family
4000
Latch Mode
Transparent
Logic Function
RS-Latch
Number of Channels
4
Output Type
3 State
Polarity
Non-Inverting
Mount Type
Surface
Minimum Supply Voltage
-5V
Pakuotės tipas
SOIC
Kaiščių skaičius
16
Maximum Supply Voltage
18V
Minimali darbinė temperatūra
-55°C
Maksimali darbinė temperatūra
125°C
Ilgis
10mm
Aukštis
1.5mm
Standards/Approvals
No
Serija
4000B
Automotive Standard
AEC-Q100
Produkto Aprašymas
The MC14043B and MC14044B quad R-S latches are constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. Each latch has an independent Q output and set and reset inputs. The Q outputs are gated through three-state buffers having a common enable input. The outputs are enabled with a logical "1" or high on the enable input, a logical "0" or low disconnects the latch from the Q outputs, resulting in an open circuit at the Q outputs.
Sandėlio informacija laikinai nepasiekiama.
€ 20,11
€ 0,419 Each (In a Tube of 48) (be PVM)
€ 24,33
€ 0,507 Each (In a Tube of 48) (su PVM)
48

€ 20,11
€ 0,419 Each (In a Tube of 48) (be PVM)
€ 24,33
€ 0,507 Each (In a Tube of 48) (su PVM)
Sandėlio informacija laikinai nepasiekiama.
48

| kiekis | Vieneto kaina | Per Vamzdelis |
|---|---|---|
| 48 - 432 | € 0,419 | € 20,11 |
| 480 - 912 | € 0,304 | € 14,59 |
| 960+ | € 0,258 | € 12,38 |
Techniniai Dokumentai
Specifikacijos
Markė
onsemiProduct Type
18 Bit D Type Latch
Logic Family
4000
Latch Mode
Transparent
Logic Function
RS-Latch
Number of Channels
4
Output Type
3 State
Polarity
Non-Inverting
Mount Type
Surface
Minimum Supply Voltage
-5V
Pakuotės tipas
SOIC
Kaiščių skaičius
16
Maximum Supply Voltage
18V
Minimali darbinė temperatūra
-55°C
Maksimali darbinė temperatūra
125°C
Ilgis
10mm
Aukštis
1.5mm
Standards/Approvals
No
Serija
4000B
Automotive Standard
AEC-Q100
Produkto Aprašymas
The MC14043B and MC14044B quad R-S latches are constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. Each latch has an independent Q output and set and reset inputs. The Q outputs are gated through three-state buffers having a common enable input. The outputs are enabled with a logical "1" or high on the enable input, a logical "0" or low disconnects the latch from the Q outputs, resulting in an open circuit at the Q outputs.