Techniniai dokumentai
Specifikacijos
Markė
NexperiaLogic Family
HC
Logic Function
JK Type
Input Type
Single Ended
Output Signal Type
Differential
Triggering Type
Negative Edge
Polarity
Inverting, Non-Inverting
Tvirtinimo tipas
Surface Mount
Pakuotės tipas
SOIC
Kaiščių skaičius
14
Set/Reset
Reset
Number of Elements per Chip
2
Maximum Propagation Delay Time @ Maximum CL
160 ns @ 2 V
Matmenys
8.75 x 4 x 1.45mm
Maximum Operating Supply Voltage
6 V
Aukštis
1.45mm
Plotis
4mm
Minimali darbinė temperatūra
-40 °C
Minimum Operating Supply Voltage
2 V
Maksimali darbinė temperatūra
+125 °C
Propagation Delay Test Condition
50pF
Ilgis
8.75mm
Kilmės šalis
Thailand
Produkto aprašymas
74HC Family Flip-Flops & Latches, Nexperia
A range of NXP Flip-Flops and Latches from the 74HC Family of CMOS Logic ICs. The 74HC Family use silicon gate CMOS technology to achieve operating speeds similar to the LSTTL family but with the low power consumption of standard CMOS integrated circuits.
74HC Family
Sandėlio informacija laikinai nepasiekiama.
Patikrinkite dar kartą.
€ 0,176
Each (In a Tube of 57) (be PVM)
€ 0,213
Each (In a Tube of 57) (su PVM)
57
€ 0,176
Each (In a Tube of 57) (be PVM)
€ 0,213
Each (In a Tube of 57) (su PVM)
57
Techniniai dokumentai
Specifikacijos
Markė
NexperiaLogic Family
HC
Logic Function
JK Type
Input Type
Single Ended
Output Signal Type
Differential
Triggering Type
Negative Edge
Polarity
Inverting, Non-Inverting
Tvirtinimo tipas
Surface Mount
Pakuotės tipas
SOIC
Kaiščių skaičius
14
Set/Reset
Reset
Number of Elements per Chip
2
Maximum Propagation Delay Time @ Maximum CL
160 ns @ 2 V
Matmenys
8.75 x 4 x 1.45mm
Maximum Operating Supply Voltage
6 V
Aukštis
1.45mm
Plotis
4mm
Minimali darbinė temperatūra
-40 °C
Minimum Operating Supply Voltage
2 V
Maksimali darbinė temperatūra
+125 °C
Propagation Delay Test Condition
50pF
Ilgis
8.75mm
Kilmės šalis
Thailand
Produkto aprašymas
74HC Family Flip-Flops & Latches, Nexperia
A range of NXP Flip-Flops and Latches from the 74HC Family of CMOS Logic ICs. The 74HC Family use silicon gate CMOS technology to achieve operating speeds similar to the LSTTL family but with the low power consumption of standard CMOS integrated circuits.